Projects
Turning ideas into reliable, scalable software.
webserver
Collaborated with three UCLA students in a Software Engineering Capstone to design and implement a web server. Team roles rotated weekly, with one member serving as team lead. Completed nine assignments over ten weeks, culminating in a self-directed final feature supported by a Design Document and Product Requirements Document.
neural-signaling
Group project for neural signaling class (will be completed soon)
riscv-processor
Developed a 32-bit RISC-V processor simulator in C++ capable of executing a subset of RISC-V instructions through a custom datapath and control unit design. Implemented instruction decoding, ALU operations, and memory access handling to accurately mimic hardware behavior. Enabled program testing through text-based instruction input, supporting both arithmetic and control-flow operations.
brewin-interpreter-v4
Developed a fully functional interpreter for the Brewin programming language over four project stages, expanding functionality from basic variable handling and printing to a statically typed system with advanced features. Implemented support for functions, control flow (if/else, loops), structs, lazy evaluation, and exception handling, as well as type checking and default return semantics.
cache-coherency
Design an LRU-based MOESIF cache coherency protocol for a four-core machine and report various statistics, including number of cache misses, hits, writebacks, broadcasts, and cache-to-cache transfers.
task_tracker
Developed a task-tracking web application with draggable task cards across “To-Do,” “In Progress,” and “Done” columns. Implemented features for card creation, editing, deletion, and drag-and-drop file uploads that auto-update descriptions. Added persistent local storage and a user-toggleable light/dark mode for enhanced usability.